1. Field of the Invention
The present invention variously relates to (i) a method of forming a (Ga, Al, In) nitride base layer on a substrate for subsequent fabrication of a microelectronic device structure thereon, (ii) to a base structure for such fabrication, including a device quality, single-crystal, crack-free base layer of (Ga, Al, In) nitride on the substrate, in which the thickness of the base layer may, for example, be on the order of 2 microns and greater and the defect density of the base layer may, for example, be on the order of 1E8 cmxe2x88x922 or lower, and (iii) to a device article comprising a device, e.g., a light emitting diode, detector, transistor, filter, semiconductor laser, etc. fabricated on such base structure.
2. Description of the Related Art
GaN and its related alloys comprising Al and In have many potential advantages, similar to the arsenide and phosphide alloys of these metals. These advantages stem from the ability to adjust the bandgap of the material by adjusting its composition, such that the bandgap of (Ga, Al, In) nitride can be adjusted from 1.9 to 6.2 eV. This characteristic of the (Ga, Al, In) nitride system lends, itself to many applications, including UV-to-green LEDs, lasers and detectors, as well as high temperature, high power, and/or high frequency electronic devices. However, to date, there has been no effective lattice-matched substrate for the III-V nitrides, as exists for GaAs and InP based alloys. This circumstance has resulted in the use of xe2x80x9cforeignxe2x80x9d substrates for (Ga, Al, In)N device structures, using substrate materials such as sapphire, lithium gallate, lithium aluminate, zinc oxide, spinel, magnesium oxide, silicon carbide, gallium arsenide, or silicon.
Of these foreign substrates, sapphire is the most commonly used for the growth of GaN-based materials and devices. However, sapphire, as well as many of the other foreign substrates, is electrically insulating with a low thermal conductivity and has a poor lattice-match to the (Ga, Al, In) nitride. As such, devices made from (Ga, Al, In) nitride grown on sapphire are limited by (1) high series resistance associated with inhibited lateral conduction of carriers through the bottom-most device layer to the active region of the device; (2) inability to dissipate heat away from the active region of the device; and (3) defects, dislocations and strain associated with the lattice-mismatch between the base layer and the substrate or between the conventional nucleation layer and the device structure.
The performance of GaN-based devices on insulating substrates is, in part, limited by the lateral conduction of carriers. An example of a basic GaN/InGaN light-emitting diode (LED) device 10 is shown in FIG. 1, which is a schematic drawing of a GaN/InGaN LED structure grown on an insulating substrate 12. In this device structure, an n-GaN layer 14 is formed on the substrate 12, with a (Ga, In)N active region 16 thereover. A p-GaN layer is deposited on the (Ga, In)N layer, and overlaid by p contact layer 20. The n-GaN layer 14 has formed thereon an n contact layer 22, as shown. In this device, as a result of the insulating character of substrate 12, current must flow laterally through the thin n-type GaN layer. The lateral flow of current through the active region of the device is limited by the carrier transport in the thin n-type GaN layer, which in turn is limited by the thickness and conductivity of such n-GaN layer. This results in high series resistance which degrades device performance, lowers device efficiency and can result in shorter operation lifetimes due to excessive heat generation in this thin n-GaN layer.
The electrical conductance of this thin n-type conductive layer 14 is, in part, limited by the growth technique used to grow the device structure, in that the growth technique limits the attainable thickness which in turn limits the electrical conductance of the layer. For instance, the thickness of GaN and related alloys grown on sapphire by the most common techniques (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)) is limited both by the slow growth rates inherent to these techniques and by the cracking of the epilayer, which develops for layers thicker than a few microns. Cracking becomes more severe for highly n-type Si-doped GaN grown by MBE and MOCVD, which causes unacceptable yield loss for a manufacturing process.
The operating characteristics and lifetime of many microelectronic devices are dependent on the operating temperature of the device. For example, the threshold current density (J) of a semiconductor laser is very sensitive to the temperature of the device, and is given by the equation:
J=J0 exp ((Txe2x88x92T0)/T0),
where J0 is the temperature independent threshold current density, T0 is the characteristic temperature of the device and T is the operating temperature of the device. This equation indicates that the threshold current density increases exponentially with the operating temperature of the device. Low threshold current density is required for laser applications, thus, being able to remove heat from the active region of a diode laser is essential to its good performance. Similar benefits are obtained for transistors (in the achievement of enhanced stability and enhanced lifetime) and detectors (in the achievement of low noise characteristics).
For substrates that have low thermal conductivity, such as sapphire, heat must be removed laterally from the device by the thin semiconductor layer. The heat flow, H, is given by the equation:
H=xe2x88x92kA(dT/dx),
where k is the thermal conductivity of the material, A is the cross-sectional area through which the heat must flow, and dT/dx is the temperature gradient. This equation shows that the ability to dissipate heat is directly proportional to the cross-sectional area, and thus for a lateral device is directly proportional to the thickness of the material. As previously mentioned, the thickness of the material grown by MBE and MOCVD is limited by slow growth rates and cracking of the material. Thus, a thick base layer would be inherently superior in removing heat from the device. As described above, keeping the temperature low improves device performance, stability and lifetime.
The density of defects and dislocations in the active region of a device affects the performance of the device. In addition, degradation and eventual failure of devices is enhanced by defects. It is thus important to minimize the number of defects in the material that forms the devices. GaN grown on sapphire, silicon carbide or other similarly poorly lattice-matched substrate, typically contains 1E10 cmxe2x88x922 dislocations. The dislocations form to accommodate the difference in lattice constant between the substrate and GaN material grown on the substrate. Defects/dislocations generated in the initial layer propagate to the active region of the device. In addition, similar dislocations, although lower in density, occur because of lattice constant differences between the individual layers of the device. By growing thick base layers which are lattice-matched to the device structure, the total defect density could be significantly reduced. Control of the composition of the base layer could be employed to minimize the dislocations generated at the base layer-device material interface. By decreasing the defect density in the device material, longer-lived, higher performance devices could be realized.
The structural benefits are also applicable to GaN-based devices grown on conductive substrates, the most common conductive substrate for GaN based materials being silicon carbide. For these substrates, the art has proposed the formation of a multi-layer GaN/AlGaN epitaxial formation by MBE or MOCVD on the silicon carbide substrates, but such multi-layer formation of a GaN epitaxial layer is difficult to achieve, due to the close control of the deposition process required in each of the sublayer formation steps of the multi-layer formation technique.
Growth of GaN and related alloys on sapphire is complicated in that the growth conditions need to be very carefully controlled during the initial nucleation stages to achieve high quality material. Typically, thin nucleation layers (xcx9c200 xc3x85) are grown at low temperature (xcx9c500xc2x0 C.) prior to the growth of the GaN device structure. The thickness, growth rate and growth temperature must be controlled to extremely fine tolerances to achieve good product material.
Existing GaN LED devices fabricated with thin n-type GaN layers also exhibit high sensitivity to electrostatic discharge (ESD). It has been posited that the ESD sensitivity may result from reduced lateral carrier transport and a high density of vertical threading dislocations in the material (e.g., on the order of 109-1010 cmxe2x88x922).
The high density of defects, and threading dislocations in particular, in III-V nitride materials are responsible for a host of problems which degrade device performance and limit device lifetime. X. H. Wu, C. R. Elsass, A. C. Abare, M. P. Mack, S. Keller, P. M. Petroff, S. P. DenBaars, and J. Speck, Proceedings of the Second International Conference on Nitride Semiconductors, (1997) 34, showed that localized growth rate changes, alloy composition and xe2x80x98V-defectxe2x80x99 formation in InGaN-based multi-quantum wells originate at threading dislocations.
H. M. Ng, D. Doppalapudi, D. Korakakis, R. Singh, and T. D. Moustakas, Proceedings of the Second International Conference on Nitride Semiconductors, (1997) 10, discloses that dislocations act as scattering centers.
S. J. Rosner, E. C. Carr, M. J. Ludowise, G. Girolami and H. I. Erikson, Appl. Phys. Lett, 70 (1997) 420, demonstrated a correlation between nonradiative recombination centers and threading dislocations. Magnesium was shown to migrate more readily away from desire regions of light-emitting diode device structures when a higher density of threading dislocations were present (N. Kuroda, C. Sasaoka, A. Kimura, A. Usui, and Y. Mochizuki, Proceedings of the Second International Conference on Nitride Semiconductors, (1997) 392).
U.S. Pat. No. 5,563,422 issued Oct. 8, 1996 to S. Nakamura et al. describes a gallium nitride-based III-V compound semiconductor device having a gallium nitride-based III-V compound semiconductor layer on a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The substrate may be sapphire or other electrically insulating substrate.
In the Nakamura et al. patent, the GaN layer provided on the substrate is formed by MOCVD. In practice of the teachings of the Nakamura et al. patent, the GaN nucleation layer thickness achievable is only on the order of 100 xc3x85. The defect density in these nucleation layers is thought to be on the order of 1E11 cmxe2x88x922 or greater, and yields a defect density of 1E9 to 1E10 cmxe2x88x922 or greater in the subsequently grown GaN layer.
U.S. Pat. No. 5,393,993 issued Feb. 28, 1995 to J. A. Edmond, et al. describes a transition crystal structure between GaN and SiC. The transition structure consists of two or three individual layers of AlGaN. The Al mole percentage in these individual layers are substantially different from each other. However, in practice of the teachings of this Edmond et al. patent, the thickness of the individual layer thickness achievable is only on the order of 1000 xc3x85, and the dislocation density is typically 1E8-1E9 cmxe2x88x922 in the subsequently grown GaN layer.
U.S. Pat. No. 5,523,589 issued Jun. 4, 1996 to J. A. Edmond et al. describes a vertical LED device on SiC substrates and includes a conductive AlGaInN buffer layer on SiC. The patent describes the formation of two graded composition layers. Such layers as mentioned hereinabove are extremely difficult to achieve.
U.S. Pat. No. 5,385,562 issued Jan. 31, 1995 to T. D. Moustakas describes a method of preparing highly insulating GaN single crystal films by MBE by a two step growth process which includes a low temperature nucleation step and a high temperature growth step. The low temperature nucleation process is carried out at 100-400xc2x0 C., resulting in an amorphous GaN nucleation layer of thicknesses between 200 and 500 xc3x85. The defect density in these nucleation layer is 1E11 cmxe2x88x922 or greater, and yields a defect density of 1E9 to 1E10 cmxe2x88x922 or greater in the subsequently grown GaN layer.
Japanese Pat. No. 60-256806 to Akasaki et al. describes an AlN nucleation step, grown at 600xc2x0 C. to thicknesses of approximately 50 nm by MOCVD. Similarly, the defect density in these nucleation layer is thought to be 1E11 cmxe2x88x922 or greater, and yields a defect density of 1E9 to 1 E10 cmxe2x88x922 or greater in the subsequently grown GaN layer.
Accordingly, it would be a substantial advance in the art, and accordingly is an object of the present invention to provide a growth technique which can produce thick, crack-free, conductive base layers which can be employed in devices to permit enhanced lateral conduction, lower dislocation density, increased heat dissipation and reduced ESD sensitivity while at the same time simplifying the growth process, in relation to prior art devices and techniques.
It is another object of the invention to provide a base material and method of forming same, which may be grown on poorly lattice-matched substrates which effectively reduce the defect density in (Ga, Al, In)N devices fabricated on the substrate.
It is yet another object of the invention to provide a base structure on which (Ga, Al, In)N devices may be grown without the excessively close tolerances in thickness, growth rate and growth temperature which are required by the thin nucleation layers of the prior art.
It is a further object of the invention to provide a (Ga, Al, In)N device article including a device such as a light emitting diode, laser, detector, transistor (e.g., field effect transistor), rectifier device, filter, etc. which is fabricated on a base structure including a base layer on a substrate.
Other objects and advantages of the present invention will be more fully apparent from the ensuing disclosure.
In one aspect, the present invention relates to a method of forming a gallium nitride base layer on a substrate for subsequent fabrication of a microelectronic device structure on the substrate, and to a base structure for such fabrication, including a single-crystal, crack-free base layer of (Ga, Al, In) nitride thereon, in which the thickness of the base layer may, for example, be on the order of 2 microns and greater and the defect density of the base layer may, for example, be on the order of 1E8 cmxe2x88x922 (1xc3x97108 cmxe2x88x922) or lower, e.g., 1E7 cmxe2x88x922 and below.
It will be understood that while the present invention is described hereinafter with specific reference to GaN base layers, such base layers alternatively could be formed of other (Ga, Al, In)N species.
In another aspect, the present invention relates to a device article comprising a device, e.g., a (Ga, Al, In)N device, on a base structure including a substrate having a base layer of (Ga, Al, In)N thereon.
As used herein, the term (Ga, Al, In) is intended to be broadly construed to include the single species, Ga, Al, and In, and well as binary and ternary compositions of such Group III metal species. Accordingly, the term (Ga, Al, In)N comprehends the compounds GaN, Al N, and InN, as well as the ternary compounds GaAlN, GaInN, and AlInN, and the quaternary compound GaAlInN, as species included in such nomenclature. Accordingly, it will be appreciated that the ensuing discussion of GaN base layers for formation of GaN-based device structures or precursors thereof, is applicable to the formation of other (Ga, Al, In)N base layers and devices.
As used herein, the term crack-free refers to a material layer in which no cracks intersect the growth surface (typically the top or uppermost surface) of the layer.
As used herein, the term base structure refers to a structure including a substrate and a base layer on the substrate, optionally with one or more intermediate layer(s) between the substrate and base layer.
As used herein, the term device precursor refers to a structure formed by carrying out at least one but less than all device fabrication steps. The precursor structure typically includes at least one epitaxial layer of the device to be formed on the base layer of the base structure. The fabrication steps may include, for example, ion implantation, etching, deposition of an epitaxial layer, patterning, masking, etc.
In one aspect, the invention relates to a method of forming a (Ga, Al, In) nitride base layer on a substrate, comprising reacting a vapor-phase (Ga, Al, In) composition, such as a (Ga, Al, In) compound or complex, e.g., (Ga, Al, In)chloride, (Ga, Al, In)bromide, etc., with a vapor-phase nitrogenous compound in the presence of the substrate, to grow a (Ga, Al, In) nitride base layer on the substrate, thereby yielding a microelectronic device foundation comprising the substrate with the (Ga, Al, In) nitride base layer thereon.
Accordingly, in reference hereafter to GaN as the base layer species, such process aspect of the invention comprises reacting a vapor-phase gallium compound such as gallium chloride with a vapor-phase nitrogenous compound in the presence of the substrate, to grow a gallium nitride base layer on the substrate, thereby yielding a microelectronic device foundation comprising the substrate with the gallium nitride base layer thereon.
The nitrogenous compound may be any suitable nitrogen-containing compound, such as ammonia, hydrazine, amines, polyamines, etc.
In a preferred aspect of such method, vapor-phase gallium chloride is formed by contacting vapor-phase hydrogen chloride with molten gallium. The molten gallium desirably is of very high purity, preferably having a purity of xe2x80x9c5-9sxe2x80x9d (i.e., 99.99999+%), and more preferably having a purity of xe2x80x9c7-9sxe2x80x9d (i.e., 99.9999999+%).
The substrate in the above method may be of any suitable material, such as sapphire, silicon, silicon carbide, diamond, lithium gallate, lithium aluminate, zinc oxide, spinel, magnesium oxide, ScAlMgO4, gallium arsenide, silicon-on-insulator, carbonized silicon-on-insulator, carbonized silicon-on-silicon, gallium nitride, etc., including conductive as well as insulating and semi-insulating substrates, twist-bonded substrates (i.e., where the substrate of crystalline material is bonded to another single crystal substrate material with a finite angular crystallographic misalignment), compliant substrates of the type disclosed in U.S. Pat. No. 5,563,428 to B. A. Ek et al., etc.
The layer of single crystal (Ga, Al, In)N may be deposited directly on the surface of the crystalline substrate, or alternatively it may be deposited on an uppermost surface of one or more intermediate layers which in turn are deposited on the crystalline substrate. The one or more intermediate layers may serve as a nucleation layer to enhance the crystallinity or other characteristics of the (Ga, Al, In)N layer, as a template for the subsequent (Ga, Al, In)N growth thereon, or as protective layer(s) from the HVPE environment.
Intermediate layer(s) may be deposited within the same reactor used for the base layer growth or pre-deposited in a separate reactor prior to base layer growth. Alternatively, the intermediate layer(s) may be formed in any other suitable manner for provision of same on the substrate, and may for example be formed separately as a discrete layer which then is bonded or placed on the substrate. Such intermediate layers may be comprised of, e.g., ZnO, SiC, carbonized silicon, (Ga, Al, In) N, and alloys of SiC and (Ga, Al, In) N.
The growth of the (Ga, Al, In)N material may be carried out in a hydride vapor phase epitaxy (HVPE) reactor. As mentioned, a protective layer may be employed to prevent decomposition of the single crystal substrate while (Ga, Al, In)N growth is proceeding. Such protective layer should be of a material favorable for (Ga, Al, In)N deposition. Examples include materials such as (Ga, Al, In)N or SiC and alloys thereof, wherein the protective layer is of a different material than the main body of the substrate, or is otherwise differently formed on the main body of the substrate, e.g., under different process conditions. The protective layer may be formed by any suitable technique such as for example sputtering, chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), ion plating, molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), metalorganic vapor phase epitaxy (MOVPE), etc.
The intermediate layer(s) serve as a suitable template for the growth of single crystal (Ga, Al, In)N. As such, it is not required that the main body of the substrate be single crystal. For example, a thin single crystal intermediate layer may be bonded to or otherwise consolidated with or formed on a polycrystalline main substrate body. The properties of the material used as the main body of the substrate can be selected to reduce stress during or after the growth and cool down process. Correspondingly, the main body of the substrate can be chosen such that the (Ga, Al, In)N material and substrate are under stress during growth, but this stress is relieved at room temperature after cool down. For example, the thermal coefficient of expansion of the material used as the main body is one property which can be chosen for this purpose.
Concerning the intermediate layer(s) usefully employed in some applications of the present invention, the initial stages of HVPE growth can largely determine the net electrical properties of the entire base structure including the intermediate layer, base layer and substrate. For instance, for GaN grown directly on sapphire by HVPE, it is common that a high density of electronic charge is present within 500 nm of the sapphire. However, if an intermediate layer is used, such as GaN grown by MOCVD, between the HVPE GaN and sapphire, this interface charge density can be reduced and the net donor concentration for the overall base structure is reduced. The interface electrical properties affect the gross electrical properties of the entire base structure. This fact can be taken advantage of in selecting the substrate and/or intermediate layer to determine the bulk electrical properties of the overall base structure.
The substrate may be patterned, e.g., with a dielectric such as SiO2 or Si3N4, or other material that nucleates substantially less well than the substrate, to permit nucleation and direct growth on specific regions of the substrate, and little to no nucleation on other regions of the substrate. Patterning could also be carried out on an intermediate layer between the substrate and the (Ga, Al, In)N material to be grown. In either case, the HVPE process may also be carried out to grow the (Ga, Al, In)N material laterally over the dielectric from the regions between the dielectric.
The base layer grown by the aforementioned method may be grown at relatively high rate, e.g., at a growth rate of at least 10 xcexcm/hour, and more preferably of at least 50 xcexcm/hour, to produce a single-crystal, substantially crack-free base layer characterized by an upper surface region with a low defect density, e.g., less than 1E8 defects/cm3, and preferably less than 1E7 defects/cm3.
The aforementioned base structure formed by the method of the invention may then be used to form a microelectronic device on the base layer, by a suitable process such as ion implantation and/or etching, or by a process including deposition of device layers by a suitable deposition technique, e.g., metalorganic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE), etc.
In another aspect, the invention relates to a base structure for fabrication of a microelectronic (Ga, Al, In) N device structure thereon, comprising a substrate and a single-crystal, crack-free base layer of (Ga, Al, In)N thereon. In some applications, the thickness of the base layer is at least about 2 microns, e.g., with a thickness in the range of from about 0.5 microns to about 1000 microns, preferably from about 2 microns to about 50 microns, more preferably from about 2 microns to about 25 microns, and most preferably from about 5 microns to about 20 microns. In other applications, the base layer desirably has a thickness of at least 10 microns, and more preferably at least 100 microns.
It will be recognized that the preferred thickness of the base layer in a given application will be substrate-dependent and will also depend on the ultimate use. For sapphire, 2 to 25 microns thick layers minimize bow and cracking while yielding low dislocation density (1E9 to 1E8 cmxe2x88x922) and smooth surfaces. Much thicker films enable much lower dislocation densities. For instance, 300 microns thick GaN grown on sapphire by HVPE yield dislocation densities of less than 1E7 cmxe2x88x922, respectively. Lower dislocation densities can be achieved for significantly thinner GaN base layers on SiC due to the closer lattice match between GaN and SiC.
In a still further aspect, the present invention relates to a GaN device structure, comprising a substrate, a single-crystal, crack-free (Ga, Al, In) N base layer on the substrate, and a GaN microelectronic device or a precursor thereof on the (Ga, Al, In)N base layer.
The low defect density material of the invention may be of significant thickness, e.g., greater than 100 microns in thickness (in the growth direction). The low defect density material has a defect density, measured on sapphire as a reference material, that is less than about 1E7 defects/cm2 at the upper surface of the material.
In another aspect, the invention relates to an unsupported base layer derived from a base structure which has been processed by suitable means and/or methods, e.g, chemical and/or mechanical in character, to remove the substrate from the base structure and leave only a free-standing (Ga, Al, In)N article, as a foundation element for subsequent device fabrication. Such substrate removal may be carried out either in situ or ex situ with respect to the growth of the base layer on the substrate in the first instance. The removal may for example by carried out ex situ by methods such as wet etching of the substrate, or laser ablation of the substrate. Such substrate removal may be carried out by separating the base layer from the substrate, for example by thermally decomposing a portion of the base layer or substrate near the base layer-substrate interface or by inducing an internal pressure at the base layer-substrate interface by a technique such as implantation of ions or other chemical species in the substrate following which the substrate is coated with the base layer and the resulting base structure is subjected to elevated temperature conditions to induce fractural separation of the substrate from the base layer, etc. Alternatively, the substrate may be removed in situ from a (Ga, Al, In)N base layer after the (Ga, Al, In)N base layer has been formed on the substrate, as for example in the manner disclosed in U.S. Pat. No. 5,679,152 issued on Oct. 21, 1997 for xe2x80x9cA METHOD OF MAKING A SINGLE CRYSTAL GaN ARTICLE.xe2x80x9d
The foregoing approaches for removing the base layer from the substrate may be usefully employed if the base layers are thick enough to be free-standing, as for example with thicknesses in excess of 100 microns, for subsequent use of the base layer as a residual support or substrate element, or with lower thicknesses, for subsequent use of the base layer as a discrete device layer.
The substrate upon which the HVPE base layer(s) are provided can be tailored to enhance the bulk properties of the overall base structure. For instance, differences in the thermal coefficient of expansion for a base layer and a substrate can cause cracking and bowing upon cool-down after growth. Thus, by using substrates with the same thermal coefficient of expansion as the base layer, cracking and bowing are minimized. Since intermediate layers can be placed upon the substrate, the substrate is not required to be single crystal. Similarly, the substrate material can be chosen so that it can be easily removed in situ or ex situ.
Other aspects and features of the invention will be more fully apparent from the ensuing disclosure.